1. Field of the Invention
The present invention relates to an analog-digital conversion circuit having a multi-stage pipeline (step flush) structure.
2. Description of the Background Art
In recent years, with the advent of advanced digital processing technology for video signals, there has been a growing demand for digital-analog conversion circuits (A/D converters) for processing video signals. Since the analog-digital conversion circuit for processing video signals must operate at high speed, a two-step flush (a two-step parallel) method has been widely employed for conventional analog-digital conversion circuits.
As the number of bits to convert has increased, however, sufficient conversion accuracy can no longer be obtained by the two-step flush method, and therefore an analog-digital conversion circuit having a multi-stage pipeline (step flush) structure has been developed. (See, for example, Japanese Patent Laid-Open No. 11-88172).
FIG. 12 is a block diagram of a conventional analog-digital conversion circuit. The analog-digital conversion circuit 101 in FIG. 12 has a 10-bit, four-stage pipeline structure.
In FIG. 12, the analog-digital conversion circuit 101 includes a sample-hold circuit 102, first to fourth stage circuits 103 to 106, a plurality of latch circuits 107, and an output circuit 108.
The first stage circuit 103 includes a sub A/D converter 109, a D/A converter 110, an operational amplifier 111a, a subtraction circuit 112, and an operational amplifier 113. The subtraction circuit 112 and the operational amplifier 113 form a differential amplifier 114. The second and third stage circuits 104 and 105 each include a sub A/D converter 109, a D/A converter 110, an operational amplifier 111, a subtraction circuit 112, and an operational amplifier 113. In the first to third stage circuits 103 to 105, the subtraction circuit 112 and the operational amplifier 113 form a differential amplifier 114.
Note however that, as will be described, the operational amplifier 111a in the first stage circuit 103 has a gain of 1 and serves as a sample-hold circuit. The operational amplifier 113 in the first stage circuit 103 and the operational amplifiers 111 and 113 in the second and third stage circuits 104 and 105 each have a gain of 2. The fourth (final) stage circuit 106 includes only a sub A/D converter 109.
The first stage circuit 103 has a 4-bit structure, and the second to fourth stage circuits 104 to 106 each have a 2-bit structure. In the first to third stage circuits 103 to 105, the number of bits (bit structure) for the sub A/D converter 109 and the D/A converter 110 are set to be equal.
Now, the operation of the analog-digital conversion circuit 101 in FIG. 12 will be described. The sample-hold circuit 102 samples an analog input signal Vin and holds the signal for a prescribed time period. The analog input signal Vin output from the sample-hold circuit 102 is transferred to the first stage circuit 103.
In the first stage circuit 103, the sub A/D converter 109 A/D-converts the analog input signal Vin. The result of A/D conversion by the sub A/D converter 109, a digital output of the high order 4 bits (29, 28, 27, 26) is transferred to the D/A converter 110 and also transferred to the output circuit 108 through the four latch circuits 107. The D/A converter 110 converts the result of A/D conversion by the sub A/D converter 109, the 4-bit digital output into an analog signal.
Meanwhile, the operational amplifier 111a samples the analog input signal Vin and holds the signal for a prescribed period. The subtraction circuit 112 subtracts between the analog input signal Vin output from the operational amplifier 111a and the D/A conversion result by the D/A converter 110. The operational amplifier 113 amplifies the output of the subtraction circuit 112. The output of the operational amplifier 113 is transferred to the second stage circuit 104.
In the second stage circuit 104, the sub A/D converter 109 A/D-converts the output from the operational amplifier 113 in the first stage circuit 103. The A/D conversion result by the sub A/D converter 109 is transferred to the D/A converter 110 and also transferred to the output circuit 108 through the three latch circuits 107. In this way, a digital output of intermediate high order 2 bits (25, 24) is obtained from the second stage circuit 104.
Meanwhile, the operational amplifier 111 amplifies the output from the operational amplifier 113 in the first stage circuit 103. The subtraction circuit 112 subtracts between the output of the operational amplifier 111 and the D/A conversion result by the D/A converter 110. The operational amplifier 113 amplifies the output of the subtraction circuit 112. The output of the operational amplifier 113 is transferred to the third stage circuit 105.
In the third stage circuit 105, the operation same as that in the second stage circuit 104 is carried out to the output from the operational amplifier 113 in the second stage circuit 104. In this way, a digital output of the intermediate low order 2 bits (23, 22) is obtained from the third stage circuit 105.
In the fourth circuit 106, the sub A/D converter 109 A/D-converts the output from the operational amplifier 113 in the third stage circuit 105, and a digital output of the low order 2 bits (21, 20) is obtained.
The digital outputs of the first to fourth stage circuits 103 to 106 simultaneously reach the output circuit 108 through the latch circuits 107. More specifically, the latch circuits 107 are provided for synchronization among the digital outputs of the circuits 103 to 106.
The output circuit 108 carries out digital correction to a 10-bit digital output Dout corresponding to the analog input signal Vin if necessary and then outputs the corrected output in parallel.
In this way, in the analog-digital conversion circuit having a multi-stage pipeline structure, the pipeline processing and amplifying function in the multiple stages allow high speed throughput (conversion frequency) and high accuracy (high resolution) to be achieved. Therefore, 8- to 12-bit structure, analog-digital conversion circuits operating with high accuracy at high speed and a conversion frequency in the range from several MHz to 100 MHz are widely used for digital video signal processing, digital communication processing and the like.
However, in the analog-digital conversion circuit having the above described multi-stage pipeline structure, the area efficiency cannot be high.